1// Copyright 2022 The Go Authors. All rights reserved.
 2// Use of this source code is governed by a BSD-style
 3// license that can be found in the LICENSE file.
 4
 5//go:build loong64
 6
 7package cpu
 8
 9const cacheLineSize = 64
10
11// Bit fields for CPUCFG registers, Related reference documents:
12// https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_cpucfg
13const (
14	// CPUCFG1 bits
15	cpucfg1_CRC32 = 1 << 25
16
17	// CPUCFG2 bits
18	cpucfg2_LAM_BH = 1 << 27
19	cpucfg2_LAMCAS = 1 << 28
20)
21
22func initOptions() {
23	options = []option{
24		{Name: "lsx", Feature: &Loong64.HasLSX},
25		{Name: "lasx", Feature: &Loong64.HasLASX},
26		{Name: "crc32", Feature: &Loong64.HasCRC32},
27		{Name: "lam_bh", Feature: &Loong64.HasLAM_BH},
28		{Name: "lamcas", Feature: &Loong64.HasLAMCAS},
29	}
30
31	// The CPUCFG data on Loong64 only reflects the hardware capabilities,
32	// not the kernel support status, so features such as LSX and LASX that
33	// require kernel support cannot be obtained from the CPUCFG data.
34	//
35	// These features only require hardware capability support and do not
36	// require kernel specific support, so they can be obtained directly
37	// through CPUCFG
38	cfg1 := get_cpucfg(1)
39	cfg2 := get_cpucfg(2)
40
41	Loong64.HasCRC32 = cfgIsSet(cfg1, cpucfg1_CRC32)
42	Loong64.HasLAMCAS = cfgIsSet(cfg2, cpucfg2_LAMCAS)
43	Loong64.HasLAM_BH = cfgIsSet(cfg2, cpucfg2_LAM_BH)
44}
45
46func get_cpucfg(reg uint32) uint32
47
48func cfgIsSet(cfg uint32, val uint32) bool {
49	return cfg&val != 0
50}